ASSET Tool Validates Design-For-Test Features

Richardson, TX -- The new DFT Analyzer from ASSET InterTech Inc. reduces manufacturing and test costs by validating the boundary-scan design-for-test (DFT) features in a circuit board design before any prototypes are assembled. In addition, DFT Analyzer determines the extent of a design's boundary-scan test coverage and recommends changes that would increase coverage.

"All too often, a new product will be delayed as it is moving out of development and into manufacturing because a circuit board can not be adequately tested and it has to be re-designed. Without adequate test coverage, the manufacturer can not be assured of the product's quality," said Alan Sguigna, vice president of sale and marketing for ASSET InterTech. "DFT Analyzer alleviates some schedule risks and reduces test and prototyping costs by alerting designers and test engineers early in the process when it is easier and much less costly to design testability into the product. Limiting or eliminating entirely the need for a board re-design saves significant costs."

The DFT Analyzer is the outcome of extensive market research and feedback from electronics manufacturers who have indicated a need for a boundary-scan DFT tool that could be incorporated into the typical design process for printed circuit boards and complement other electronic design automation (EDA) systems.

DFT Analyzer is made up of three tools which are employed at different stages in product development. First, as the schematics are being developed, the automated Checklist is used to query a designer or a design team about the testability features that have been included in the design. These questions are based on sound DFT principles derived from ASSET's many years of working with board designers to optimize boundary-scan test coverage. In addition, design practices specific to the organization can be reflected in the Checklist to ensure consistency across all of a company's designs.

Next, the DFT Analyzer's Design Validation tool can be launched after computer aided design (CAD) information has been compiled. CAD data is imported into DFT Analyzer so that the Design Validation tool can determine whether any pre-established DFT rules have been broken or overlooked. The tool recommends a solution if it encounters a broken rule.

DFT Analyzer's third tool, Test Coverage Analysis, is engaged during the final stages of design before first prototypes of the board are manufactured. This tool determines the extent of boundary-scan test coverage when certain types of tests, such as interconnect, memory and other tests, are run on the circuit board. In addition, the report contains information on which of the on-board test pads that are used by in-circuit test (ICT) system can be eliminated by substituting a boundary-scan test for the ICT operation. Eliminating ICT test points saves board space and reduces the complexity and cost of an ICT test fixture. In addition, the Test Coverage Analysis module can output its results to DFT Analyzer's design browser which graphically displays the available test coverage in a schematic view.

The final output of DFT Analyzer is a complete boundary-scan description of the design that can be imported directly into ASSET's boundary-scan test generation tool in ScanWorks, the company's JTAG system. With minimal additional effort, a set of boundary-scan tests can be optimized for the first prototype boards and then reused through the manufacturing process and into system test and field support.

SOURCE: ASSET InterTech, Inc.