ASSET's Design-For-Test Lab Validates JTAG Capabilities In Chip And Board Designs
The lab will offer a free analysis of pre-prototype designs and advice to ensure that the JTAG infrastructure can be effectively deployed in its traditional structural test applications as well as in advanced applications that take advantage of the JTAG infrastructure, such as the testing of high-speed AC-coupled serial buses (IEEE 1149.6), Intel™ Internal Built In Self Test (IBIST), system-level remote JTAG testing, concurrent programming based on the IEEE 1532 standard and others.
"Today there are several test and programming methodologies which depend upon an effective boundary-scan infrastructure. Without a properly designed JTAG infrastructure, these advanced methodologies can't perform their functions. We expect that as board designs continue becoming denser and as chip geometries shrink even smaller, new applications for JTAG will only increase in the future," said Arden Bjerkeli, ASSET's director of support. "Quite often, design or verification engineers are not familiar with some of the finer points of JTAG design-for-test. The DFT Lab can strengthen the JTAG infrastructure in chip and circuit board designs before samples or prototypes are ever produced. That means that development and production schedules can be maintained and expensive re-designs following prototype production will be avoided."
ASSET's first DFT Lab is located in Silicon Valley at 2033 Gateway Place, Suite 600, San Jose, CA 95110. The services of the lab are available to first-time users of boundary scan. Scott Creekpaum has been named manager of the lab. The free analysis and design recommendations will be performed with ASSET's DFT Analyzer, the industry's only tool that automatically verifies the JTAG testability of board designs. The accuracy of a chip design's Boundary-scan Description Language (BSDL) file will be verified with the BSDL Validation Service, a collaborative effort of ASSET and Agilent Technologies, Inc. In addition, other tools can be applied to board and chip designs to validate their JTAG capabilities.
"Because of our automated board-design validation tool, DFT Analyzer, in most cases we can perform a thorough and in-depth design review very quickly," Creekpaum said. "In fact, what previously took days or even weeks to do manually can now be completed with DFT Analyzer in a matter of hours. Moreover, the lab's reports are much more than simple test coverage reports. Our reviews offer design recommendations that engineers can implement to improve test coverage or to ensure that the JTAG infrastructure has been implemented effectively so that other methodologies can run on top of it."
SOURCE: ASSET InterTech, Inc.