Cadence Adds IDDQ Testing Capabilities

Cadence Design Systems announced that it has added advanced IDDQ test generation capabilities and statistical fault analysis to its Affirma Verifault XL fault simulation software. These enhancements reduce test development time for complex system-on-a-chip (SOC) designs.

Fault simulators are used to create test vectors for detecting manufacturing faults in an integrated circuit (IC) or application specific integrated circuit (ASIC). IDDQ test generation capability allows customers to select the minimum test vectors for maximum fault coverage using sophisticated IDDQ technology. It allows the user to compute IDDQ fault coverage and generate fault reports for diagnostics. This new functionality is easy to use and operates on the customer's existing Verilog design database.

A second feature reduces test development time by as much as 50% by providing statistical fault analysis capability. Using the STAFAN algorithm, undetectable faults are dropped from the fault list through the analysis of logic simulation.

The Affirma Verifault XL software provides fast and accurate fault simulation. It is built on the Verilog-XL simulation engine and is the only fault simulator with full timing capability and "golden" sign-off with most ASIC vendors. It uses Verilog hardware description language (HDL) and has the ability to run directly from Verilog libraries. It also has the ability to propagate faults through the Verilog-XL simulator at the register-transfer level (RTL) of design.

The Affirma Verifault XL fault simulator is available on UNIX-based workstations from Sun Microsystems and Hewlett Packard. It is list priced at $50,000 (U.S.) for a master floating license, or $12, 500 (U.S.) for a distributed floating license. New features are currently in beta and will be available beginning in December 1998 at no additional cost to customers on software maintenance.

Cadence Design Systems Inc. Phone: 408-428-5795.