Cascade Microtech To Discuss Latest Breakthroughs In 3D Device Test Technologies At Fall Test Conferences
Experts to Present at The International Known-Good Die Conference, The International Test Conference, and The IEEE 3-D Test Workshop in Austin, Texas
Beaverton, OR--(Marketwire) - Cascade Microtech, Inc. (NASDAQ: CSCD), a global leader in microelectronic test, today announced it will discuss results of extensive research in high-density wafer probe technology at three upcoming test conferences this fall targeted at 3D device testing. The results show that evolutionary scaling of Cascade Microtech's Pyramid Probe® technology can achieve the mechanical, electrical, and economic requirements of probing fine-pitch through-silicon vias (TSVs) for known-good die (KGD) sorting of 3D chips before stacking.
At the first IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits held this year in conjunction with ITC, Ken Smith, principal engineer in Cascade Microtech's Technology Development Group will challenge the assumption that probing TSVs is impossible, highly risky, or prohibitively expensive with a technical paper entitled "KGD Probing of TSVs at 40µm Array Pitch" to be presented during Session 4 at 8:00 a.m. on Friday, November 5. Mr. Smith will discuss how contacting at TSV pitches is practical with evolutions of existing probe technology, and how new probe technology enables test strategies which probe some or all of the TSV pads, whether on the face or back of the wafer.
Cascade Microtech's Chief Technical Officer Eric Strid will participate in ITC Panel 5 entitled "3-D Test - A New Paradigm in Semiconductor Test" on Thursday, November 4 at 2:00 p.m. at the Austin Convention Center. This panel hopes to help surface the new 3-D test paradigms in the effort to first recognize and agree on the challenges, followed by a list of ideas and tasks required by the industry to solve them. The panel will debate the DFT and test methodology options for a target application: a 3-D massively parallel processor with stacked memories. Mr. Strid will be joined in this panel discussion by senior executives from IBM, Cadence, Qualcomm, Georgia Institute of Technology, AMD, and others.
On October 28, just prior to ITC, Cascade Microtech's Michael Wright, general manager of Test Sockets, will participate in the KGD Packaging and Test Conference panel discussion at 4:00 p.m. entitled "Is KGD Ready for TSV?" moderated by Jan Vardaman, TechSearch International.
"Cascade Microtech continues its aggressive exploration of leading-edge technologies for addressing emerging customer requirements in 3D test, and we appreciate the opportunity to engage in active dialogue with our peers at ITC, KGD, and the 3D-Test Workshop," said Michael Burger, president and CEO, Cascade Microtech, Inc. "Our growing knowledge of complex test requirements for 3D test and measurement is providing early insight into the development of probe equipment, and we believe we are poised to meet the measurement needs of semiconductor developers and manufacturers as 3D ICs ramp over the next two to three years."
About Cascade Microtech, Inc.
Cascade Microtech, Inc. (NASDAQ: CSCD) is a worldwide leader in the precise electrical and mechanical measurement and test of integrated circuits (ICs) and other small structures. For technology businesses and scientific institutions that need to evaluate small structures, Cascade Microtech delivers access to electrical data from wafers, ICs, IC packages, circuit boards and modules, MEMS, 3D TSV, LED devices and more. Cascade Microtech's leading-edge semiconductor production test products include unique probe cards and test sockets that reduce manufacturing costs of high-speed and high-density semiconductor chips. For more information visit www.cascademicrotech.com.
SOURCE: Cascade Microtech