Product/Service

Chip Design Test Solution

Source: Genesys Testware
Genesys Testware features enhancements to Memory BistCore, a synthesizable memory Built-In Self-Test (BIST) core library

Genesys Testware features enhancements to Memory BistCore, a synthesizable memory Built-In Self-Test (BIST) core library. Memory BistCore supports Built-In Self Test Diagnosis and Repair (BISTDR) of embedded dynamic memories (DRAM). It supports word, page and burst, memory access modes, customized data retention tests, and self repair.

Memory BistCore provides BIST for SRAMS, FIFOs and DRAMS, an architecture that supports all memory test algorithms, and features like fault isolation. It offers a built-in support scan and a capability to directly interface with any IEEE 1149.1 compatible Test Access Port (TAP) controller. The circuit for DRAMS can be operated in six possible ways corresponding to word, page and burst access modes, and data retention test application.

Genesys Testware, Inc., 181 Ottawa Way, Fremont, CA 94539. Phone: 510-661-0791; Fax: 510-498-8734.