Chip Express Endorses PrimeTime for Sign-off on Current and Next-Generation CX Technology
PrimeTime provides our customers with timing analysis technology as they design their next-generation ASIC products, said Jonathan Park, director of methodology at Chip Express. "PrimeTime's advanced built-in delay calculator also offers timing consistency throughout the design flow, making the tool an ideal candidate for our future golden delay calculator."
Chip Express currently employs a wide range of Synopsys tools including Design Compiler and Formality. These tools support Chip Express and their customers in providing a smooth migration of the design from the prototyping phase through initial volume, into high-volume ASIC production. As the company introduces ASIC families with million-gate devices, PrimeTime's timing analysis is used for analysis of these increasingly complex designs.
Chip Express manufactures fast-turn ASIC prototypes to service the needs of electronic system designers. The company's customization technologies are employed for configurable system-on-chip applications.
Synopsys' PrimeTime product is a stand-alone, full-chip gate-level static timing analysis and sign-off tool targeted for complex multimillion-gate IC designs. Both Unix and Windows NT platforms are supported. Its libraries and delay calculation sub-system -- including IEEE 1481-delay calculation language (DCL) and Tcl command interface -- are the same as those used with Synopsys' Design Compiler and Chip Architect tools.
Synopsys is a supplier of electronic design automation (EDA) solutions to the global electronics market. The company provides design technologies to creators of advanced integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting services and support to its customers to streamline the overall design process and accelerate time to market.
Synopsys, Inc. Phone: 650-584-1330; Email - Kurt Mumma: mumma@synopsys.com
Edited by Paul O'Shea