CST To Build IBM Designed, JEDEC PC100/PC133 DIMM Clock Reference Board

CST, Inc. (Dallas, TX) will manufacture and distribute the PC100/PC133 DIMM clock reference board designed by IBM Micro Electronic Division. The clock reference board can serve as a test vehicle for module producers (to tune the module assembly during validation), and as a qualification vehicle for system producers. The board consists of a clock generator and a seven outputs buffer.

Four of the clock signals go to the DIMM module socket while other lines go to the on-board industry defined reference net circuit. Oscilloscope waveform measurement is made at the DRAM and compared against the measurement at the reference net for time delay and skew.

CST will be building all the boards in one batch to ensure consistency. A golden board will be maintained to support future builds.

Current JEDEC and industry de-facto standards do not provide a method for ensuring memory module (SDRAM/register) clock timing accuracy. Previous JEDEC and Intel specifications define the clock structure, in good detail, but provide no measurement method or delay value at the DIMM-level. PC100-compliant DIMMs, from major suppliers, vary by greater than 1ns (10% of cycletime!) in clock arrival at SDRAM. Computer system manufacturers have selected various clock delay measurement solutions and specs, driving suppliers to have inconsistent clock delays. With increased SDR clock speeds, as well as with DDR DIMMs emerging, improved clock definitions and measurement techniques are needed.

CST, Inc. 2336 Lu Field Road, Dallas, Texas 75229, USA. 972-241-2662, e-mail cst@simmtester.com