Design for Test

DC Expert Plus from Synopsys provides a design-for-test methodology with a synthesis-based design flow in one tool. It includes constraint-optimized scan insertion, hierarchical DFT, and 1-pass scan synthesis.

DC Expert Plus allows implementation in a hierarchical flow for test. The chip design is done hierarchically with design done by synthesizing on different modules and then assembling the modules to create a full chip.

Starting from HDL, the tool can operate on modules or an imported netlist, or reuse blocks with existing scan. It can synthesize a design from HDL directly to optimized, testable gates (1-pass scan synthesis), or insert and route scan chains into an existing design (constraint-optimized scan insertion). Scan chains can be inserted at the module level, then the chains stitched together at the chip level after full-chip assembly.

Synopsis Inc., 700 East Middlefield Rd., Mountain View, CA 94043. Phone: 650-962-5000.