Electroglas Creates Sort-Floor Solution for Inspection, Test and Analysis of Bumped Wafers

Electroglas Inc., a supplier of process management tools for the semiconductor industry, unveiled its bumped wafer sort solution, the first-of-its-kind integration of automated inspection, probe and yield management tools for bumped wafer testing and analysis.

The bump wafer sort solution enables Electroglas' QuickSilver automated inspection system to share bump inspection wafer maps with Electroglas' new EG4/200 and EG5/300 probers as well as its Horizon 4090 line of probers via a network. This communication flow allows the probers to skip testing die that have been identified as defective by the QuickSilver system. The QuickSilver inspection results are also transferred to Knight Technology's YieldManager and Spatial Pattern Recognition (SPaR) software where they can be accessed at the wafer manufacturing level, allowing customers to identify and correct defective steps in the process.

"The strategic value of the bump wafer sort solution is that Electroglas provides customers with an integrated set of process management tools that allow them to improve yields and decrease total cost of ownership," explains Curt Wozniak, president and CEO of Electroglas.

"The wafer manufacturing, test and packaging processes continue to increase in complexity as integrated circuits are packed with more features," Wozniak says. "Electroglas firmly believes that to keep pace with these complexities, data gathered during each step in the process must be shared both upstream and downstream."

Following the wafer manufacturing process, solder or gold bumps are fabricated on the wafer to form the interconnection between the chip and package. This bumping process can produce bumps that are the wrong size or shape, in the wrong place or shorted together. These defective bumps can cause yield loss at the packaging step even though they test "good" at wafer probe. Defective bumps can also cause damage to expensive probe cards and costly downtime for the tester. Bump damage caused during the probing process itself can also be a source of yield loss.

To address these issues, the QuickSilver inspection system visually inspects 100 percent of the wafer bumps using TDI scanning technology. After inspecting the wafer for visually good and bad die, QuickSilver stores its results in the SORTnet database that can be accessed by both the inspection systems and probers. Electroglas' SORTview software turns these results into a wafer map that it shares with the EG4/200 and EG5/300 prober. The wafer is moved from the QuickSilver inspection system to the prober for testing. Using the wafer inspection maps, the prober skips testing die that have already been identified by QuickSilver as defective.

The benefit of allowing prober access to the inspection data is that probe card damage, due to testing bad bumps, is significantly reduced. In addition the entire process becomes more efficient because the prober does not spend time testing bad die, and the likelihood of packaging bad die is greatly reduced.

In some instances it may be valuable for the wafer to be re-inspected on the QuickSilver system after probe to check for bump damage. In this case the original inspection map from the QuickSilver system can be combined with the test results map generated on the prober to generate a final composite map of good and bad die.

Inspection results from QuickSilver can also be accessed for analysis by Knights YieldManager and SPaR software systems. YieldManager is a yield management system that helps engineers quickly determine sources of semiconductor yield loss. SPaR allows for user-defined classification of defect wafer maps. By integrating the QuickSilver data into these systems, customers can feed data both upstream (to the fab) and downstream (to the packaging and assembly area) to help optimize the entire process. The tools can be used to help correct defects, improving yield and lowering cost of ownership.

"Industry forecasts predict that more than 20% of all ICs will use bump technologies within the next five years, and for high-end applications, such as microprocessors, it is expected to be even higher," says Joe Savarese, VP of business development and general manager of Electroglas' Inspection Products Division.

"This shift in the industry is being driven by products with increasing space restrictions and electrical performance requirements, such as those in the portable applications market," Savarese says. "The bumping process brings with it a whole new set of demands, a subset of which Electroglas is successfully addressing by offering this complete bump sort-floor solution."

Electroglas' bump wafer solution is a complete package for managing the bump sort floor, while the inspection system, probers, networking software and yield management software all use a common format for sharing data over a network.

A demonstration of the bumped wafer sort solution will be at SEMICON West '99 at the Electroglas' booth no. 11221.