GOEPEL Electronic Upgrades FPGA Embedded Instruments For Multi-Channel Bit Error Rate Test

At Embedded World 2014 GOEPEL electronic announces the introduction of new features for parallel Multi-Channel Bit Error Rate Tests (BERT) for its IP-based ChipVORX technology.

At Embedded World 2014 GOEPEL electronic, world’s leading provider of JTAG/ Boundary Scan solutions IEEE1149.x, announces the introduction of new features for parallel Multi-Channel Bit Error Rate Tests (BERT) for its IP-based ChipVORX technology.

The highly automated solution enables FPGA Embedded Instruments utilization in the form of special softcores for the test and design validation of multi-channel high-speed I/O and high-performance serial bus systems as e.g. PCI Express x2/x4/x8/x16.

Users can now evaluate the transmission channel quality via parallel measurement of the bit error rate on all channels at the same time. A graphical evaluation via eye diagram is possible to support design validation.

ChipVORX takes over the complete process flow starting with Target FPGA programming, IP to pin configuration, instrument control as well as data processing and the final IP unloading. In the debug mode, the BERT parameters can be changed interactively for immediate effect without design synthesis. Integrated in the software SYSTEM CASCON, an Automatic Application Program Generator (AAPG) for automatic test procedure generation is available. That makes the utilization of the new BERT solution highly efficient and user-friendly.

"With these new ChipVORX models for Bit Error Rate Test we are now able to cover even most complex high-speed designs with serial multi-lane bus systems of highest band width“, says Bettina Richter, Marketing Manager at GOEPEL electronic.

"By the parallel instrumentation it is not only possible to recognize interactions between channels during design validation, but also to reduce test time to a minimum. Simultaneously, we push the use of FPGA Embedded Instruments as a pathbreaking solution for quality insurance of access critical designs“.