IEEE 1394 as a T&M Bus
•IEEE 1394 Features
•IEEE 1394 and VXIbus
•Making it Easier
The Test and Measurement industry is moving – from T&M-specific I/O standards to desktop computer I/O standards. For the first time since the invention of HP-IB, there is an external computer peripheral bus that meets the demanding needs of high-performance measurement systems. That bus is IEEE 1394, a high-speed serial bus based on Apple Computer's "Firewire" bus. Its speed is 400 Mb/s, and it also features and multi-drop characteristics.
Last year, Hewlett-Packard introduced the HP E8491A VXIbus interface, the first IEEE 1394 product in T&M. National Instruments introduced their version of an 1394-VXIbus interface. Since then, a few other products have hit the market. Continuing the trend, HP recently introduced an enhanced version of their IEEE 1394-VXIbus interface, the E8491B, which is said to move data five times faster than its predecessor. On the standards front, the 1394 Trade Association formed an Instrumentation and Industrial Control working group. The definition of standard IEEE 1394 protocols for instrumentation and industrial control are nearly completed.
IEEE 1394 is not really a bus, as it uses point-to-point cabling, with each node acting as a repeater. The codes are connected in an arbitrary tree topology, as illustrated in Figure 1,with up to 63 nodes, or devices. Each cable segment may be a maximum of 4.5 meters long, with a maximum of 16 hops, or cable segments separating any two devices. Each cable includes two differential pairs for delivering data and clocking information, and a power-ground pair. As currently defined, the bus operates at 100, 200, and 400 MB/s.
IEEE 1394 defines physical, link, and transaction level services. The physical, or PHY, layer is typically implemented as single integrated circuit, having both analog and digital capabilities. It manages bus reset activities, receiving and transmitting data, synchronizing an incoming bit stream to a local clock and transmitting the data out other ports, and bus arbitration. The link layer is also normally implemented in hardware, as a digital-only integrated circuit or as a part of a larger digital device. The transaction layer is usually implemented as software.
Data moves across the bus in packets that include headers, 1-2048 bytes of data, and CRC words for error detection. These may be either isochronous or asynchronous packets. Isochronous packets deliver data at a constant, guaranteed rate. They are sent using channels,, and may be received by any device listening to that channel. Receivers of isochronous packets do not confirm, or acknowledge, receipt of the packets. Asynchronous packets form the basis of a reliable transport mechanism, since they are always acknowledged. However they do not provide guaranteed data rate rates. Asynchronous packets are sent to particular addresses. Each device, or node, has a 48-bit address space, plus a six-bit node ID, and a 10-bit bus ID. The node IDs are automatically determined at each bus reset. No address switches are required.
Although invented for audio-visual applications, IEEE 1394 is well suited for T&M applications. It has already been accepted as a cost-effective means to connect a PC to a VXIbus system. In this application, the 1394 bus efficiently moves data between a PC and the VXIbus backplane. This data can be simple register operations, block data moves, or messages. Simple register operations are single-word reads or writes of registers or memory locations. Block data moves are multiple reads or writes of contiguous memory locations or FIFO registers. Messages are character strings transferred to and from VXIbus message based devices via the VXIbus byte transfer protocol.
Figure 2 shows a block diagram of the HP E8491A, the first IEEE 1394 to VXIbus interface. It includes six major functional blocks:
- IEEE 1394 Interface.
- Data Buffer.
- The VXI Interface.
- Processor.
- Clock Routing
- Trigger Management
The 400 Mb/s IEEE 1394 interface includes a PHY device, a link device, and three connectors, allowing tree-like system topologies. Thy PHY interface is DC isolated from the system ground, and can draw its power from either the IEEE 1394 cable or the VXIbus backplane. When the VXIbus system is powered up, HP E8491 supplies backplane power to the PHY interface. When the cardcage is not powered, the PHY interface draws power from the IEEE 1394 bus, maintaining the capability to pass data between its three ports.
In order to accommodate the speed mismatch between the synchronous IEEE 1394 bus and asynchronous VXIbus devices, the Data Buffer provides temporary storage of data moving between them. This buffer has three data ports, with FIFOs dedicated to the Link device, the VXIbus interface, and the E8491's processor. The buffer supports simultaneous, full speed transfers at all three ports, and can store up to 128kB. With these resources, IEEE 1394 transactions can be overlapped with VXIbus transactions, allowing maximum utilization of both buses.
The VXI Interface moves data between the Data Buffer and the VXIbus backplane. It supports 8, 16, 32, and 64 bit data transfers on the VXIbus. It includes 128 kB of shared RAM, and has all the features required of a Slot 0, VXIbus commander. Its state machines can perform single read/writes, multiple read/writes, BLT (VMEbus Block Transfer mode) read/writes, and IRQ Status/ID reads. The VXIbus interface includes a Data Mux VXIbus interface is the Data Mux, which multiplexes data from the fixed, 32 bit wide Data Buffer bus to the variable 8-64 bit wide VXIbus. It also performs the classic byte swapping between big-endian and little-endian data formats.
The Processor section manages the IEEE 1394 interface, both interpreting incoming packets, and building outgoing packets. It also programs the VXIbus interface to execute various backplane operations. It executes the word serial protocol for communication with VXIbus message based devices. It is responsible for programming the FPGAs (field programmable gate arrays) in the data buffer, VXIbus interface, and trigger management circuits. This section includes a microprocessor, memory, and miscellaneous support logic. All program and FPGA code is stored in flash ROM so that it can be updated over the IEEE 1394 bus.
The Clock Routing circuit drives the backplane 10 MHz CLK10 signal, and the Clk Out signal on the front panel, from either the external Clk In signal or an internal oscillator.
The Trigger Management section allows the processor to drive and sense trigger events. It also provides for the routing of trigger signals between the front panel and the backplane trigger lines.
To accommodate changing requirements and technology, the HP E8491A was designed for easy field upgrades. All the unique hardware functions are implemented in FPGAs. The code for both the microprocessor and the FPGAs are stored in FLASH ROM. All of the FLASH ROM may be programmed over the IEEE 1394 bus.
Hewlett-Packard's second generation IEEE 1394 to VXIbus interface, the HP E8491B, features a 14MB/s sustained block transfer rate. It uses the same VXIbus module as its predecessor; the HP E8491B ships with a host adapter card (the PCI to IEEE 1394 interface installed in the computer). This allows the transport of 2 kB data packets – the HP E8491A was limited to 512 byte packets. The raw backplane speed is supporting a raw transfer rate of 66.6 MB/s (for D64 transfers). An HP E8491A can be upgraded to the same performance with the purchase of the new host adapter and the installation of the latest HP I/O library software.
Gregory A. Hill is a registerd professional engineer in the State of Colorado with a BSEE and an MSEE from Texas Tech University. Greg has served as a product development engineer at Heweltt-Packard's Measurement Systems Division since 1979. He has been president and secretary of the VXIbus consortium and has been a major contributor to the VXI specification.