Product/Service

Memory Test Option

Source: Teradyne Inc.
The INTEGRA J750 is a Memory Test Option (MTO) that is a highly-integrated series of systems designed for testing devices in the low-end and mid-range very large scale integration (VLSI) markets, such as field programmable gate arrays (FPGAs), PLDs, micro
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The INTEGRA J750 is a Memory Test Option (MTO) that is a highly-integrated series of systems designed for testing devices in the low-end and mid-range very large scale integration (VLSI) markets, such as field programmable gate arrays (FPGAs), PLDs, microcontrollers, and digital audio/video devices. The test option provides the hardware and software needed to test large embedded FLASH, dynamic random access memory (DRAM), read-only memory (ROM), and EEPROM found on VLSI devices.

The system provides hardware and software memory test tools, including a complete hardware algorithmic and non-algorithmic pattern generator, address scrambling and topological inversion. It also features capture memory for bitmap, debug, and redundancy analysis. The system also supports all standard and non-standard memory tests.

Teradyne Inc., 321 Harrison Ave., Boston, MA 02118-2238. Phone: 617-482-2700.