Mentor Graphics And Cadence Partner

Mentor Graphics Corporation's Design-For-Test (DFT) Division and Cadence Design Systems today announced an agreement to integrate their industry-leading DFT and synthesis products, enabling design engineers to insert test circuitry and start automatic test pattern generation (ATPG) in conjunction with initial synthesis. Design engineers can leverage this integration to reduce the cost and improve the quality of new systems by shortening the amount of time required to achieve reliable functionality for multimillion-gate ASICs and ICs.

The result of the agreement is the integration of Mentor Graphics FastScan ATPG technology with one-pass scan insertion technology, available in the Cadence BuildGates synthesis software. This combination will allow users to automatically output the files required to run the FastScan tool for test generation during test synthesis, thereby enabling ATPG tests to become part of the single-pass test synthesis flow. This automation eliminates the extensive hand-editing process, employed by traditional methods, required to move from synthesis to manual test.